Performance

本文将介绍RISV-V性能测试过程中常用的一些方式

RTC Timer

RISC-V Core中有一个Real time clock timer (mcycle)，使用方式如下：

/* Defines to access CSR registers within C code */
#define read_csr(reg) ({ unsigned long __tmp; \
        asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
        __tmp; })

#define write_csr(reg, val) ({ \
        asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })

// Clear timer
write_csr(mcycle, 0);

VVDRV_qtm_setTestResult(result);

// Get MCYCLE

Reference